With the evolvement of flash process, a flash protocol standard and a frequency, an interface mode, a timing requirement, and the like of a flash bus interface continuously change. To enable a flash interface controller to adapt to various flashes, a current status of the evolvement of a flash technology brings an extremely large challenge to flexible and scalable design of the flash interface controller.
The flash interface controller usually includes a channel management module and a channel. The channel management module distributes an operation command to a corresponding channel. The channel parses the operation command, and sends a bus operation that is finally obtained through the parsing to a flash bus connected to the channel. Each physical flash bus is configured to connect a plurality of flash dies, and a die is a smallest storage unit in a flash.
In the related art, the flash interface controller uses a full-logic implementation or a software implementation when processing the operation command.
In the full-logic implementation, processing logics of physical modules (including the channel management module and modules in the channel) in the flash interface controller are fixed, each physical module uses the fixed processing logic to process a command delivered by a physical module at an upper layer. In this manner, the processing logics of all physical modules are fixed in advance, and when a protocol of the operation command changes, a procedure of parsing the operation command also changes. As a result, the physical module whose processing logic is fixed cannot adapt to an operation command of a latest protocol, and therefore has poor flexibility.
In the software implementation, a micro-central processing unit (CPU for short) is added to the channel management module in the flash interface controller. When the protocol of the operation command changes, a software logic in the CPU can be modified. The operation command is parsed by using a software logic that is obtained after the modification and that adapts to the latest protocol. An instruction obtained after the parsing is delivered to the physical modules in the channel. The physical modules in the channel still perform processing based on the processing logics that are fixed in advance. The CPU needs to participate in parsing of each operation command. Therefore, in an application scenario of concurrency of a plurality of channels and a plurality of dies, there is a very high requirement on performance of the CPU, and a plurality of CPUs may need to perform concurrent processing. However, the plurality of CPUs cause relatively large power consumption and area costs. In addition, a bus operation that is finally obtained through the parsing in the channel needs to meet a flash bus interface standard. When the flash bus interface standard changes, the fixed processing logic in the channel cannot adapt to the flash bus interface standard, still causing poor flexibility.